Passive Components and Circuits
Interconnections Techniques in Electronics
New Methods of Testing PCB Traces Capacity and Fusing authors Norocel Codreanu, Radu Bunea, and Paul Svasta
TIE 2010 Event - student's contest article by Andreea Bonea, Press Officer of IEEE CPMT Student Branch Chapter of the Politehnica University of Bucharest, Romania
Interconnection Techniques in Electronics (TIE) Event – International Student Professional Contest 20th Edition article by Cristina Marghescu, IEEE CPMT Student Branch Chapter of the Politehnica University of Bucharest, Romania
The first edition of the third decade of the TIE event article by Norocel Codreanu, Andreea Bonea
Interconnection Techniques in Electronics (TIE) International Professional Student Contest in the field of advanced PCB design article on LinkedIn by Norocel Codreanu, Andreea Bonea
Svasta Paul | email@example.com
Codreanu Norocel | firstname.lastname@example.org
Ionescu Ciprian | email@example.com
Drumea Andrei | firstname.lastname@example.org
Ioan Plotog | email@example.com
The INTERCONNECTION TECHNIQUES IN ELECTRONICS (TIE) contest is a student professional contest whose objective is to promote technological computer aided design (CAE-CAD-CAM) of electronic modules. This contest brings together students from many University Centers since 1992. Students have a greatopportunity by taking part in this contest. A good organization and a total transparency during the contest are the main coordinates proving professionalism and fair-play among students keen on electronic packaging.
TIE 2009 was held in April 2009 and the local phases took place in every University Center in March 2009. In the finals, competitors were the students with the best results in the qualification phases. TIE 2009 was organized this year between 9 and 12 April 2009 , in Galati.
Disclaimer: Information is provided "as is" without warranty or guarantee of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise.
Please use this information at your own risk and any attempt to use this information is at your own risk we recommend using it on a copy of your data to be sure you understand what it does and under your conditions. Keep your master intact until you are personally satisfied with the use of this information within your environment.
"Cadence is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134."